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MIK2152 Video Decoder Preliminary Specification
(Rev. 1.4)
February 2007
MIKTAM Technologies, Inc.
Confidential
REVISION HISTORY: (last updated on February 27, 2007) 1. Rev 1.0 with the updated registers details - Tom 01/09/06
Date 9/3/05 3/16/06 8/21/06 2/26/07
Revision 1.0 1.1 1.2 1.4
Description Published spec Revise Pin 3 & pin 7 Revise supported video formats; document built-in color bars Add chip level block diagram
In-charger Tom Tom Tom Tom
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MIK2152 Preliminary Specification (Rev. 1.4)
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1.
Introduction
The MIK2152 device is an ultra-low power NTSC/PAL video decoder. Available in a popular space saving 32-pin TQFP package, the MIK2152 decoder converts NTSC, PAL video signals to 8-bit CCIR 656 format. Discrete syncs are also available. The MIK2152 decoder has an ultra-low power consumption, around 150 mW of power in typical operation and consumes less than 1 mW in power down mode, which increasing battery life in hand-held application. The decoder uses just one crystal for all supported standards. The MIK2152 decoder can be programmed using an I2C serial interface. The decoder uses a 1.8 v power supply for its digital and analog circuits and 3.3 v power supply for its I/O. The MIK2152 decoder converts base band analog video into digital YCbCr 4:2:2 component video. Composite and S-video inputs are supported. The MIK2152 decoder includes one 10-bit analog-to-digital converter (ADC) with 2x sampling rate. Sampling is CCIR 601 (27.0 MHz, generated from the 27.0 MHz or other common used crystals). The output format can be 8-bit 4:2:2 or 8-bit CCIR 656 with embedded synchronization. Complementary 5 line adaptive comb filtering is available for both the luma and chroma data paths to reduce both cross-luma and cross-chroma artifacts. Video characteristics including hue, contrast, brightness, saturation, and sharpness may be programmed using the industry standard I2C serial interface. The MIK2152 decoder generates synchronization, blanking, lock, and clock signals in addition to digital video outputs. The MIK2152 decoder detects copy-protected input signals according to the MacrovisionTM standard. The main blocks of the MIK2152 decoder include: Sync detector ADC with clamping and Automatic Gain Control (AGC) Y/C separation using 5-line adaptive comb filter Chroma processor Luma processor Video clock/timing processor and power-down control I2C interface MacrovisionTM detection for composite and S-video
1.1
Features
Accepts NTSC (M), PAL (B, D, G, H, I, M, Nc) Support CCIR 601 standard sampling High-speed 10-bit ADC Two composite inputs or one S-video input Fully differential CMOS analog pre-processing channel with clamping and automatic gain control (AGC) for the best signal-to-noise performance. Ultra-low power consumption: around 150 mW typical Power-down mode: <1 mW
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Popular 32-pin TQFP Using I2C for brightness, contrast, saturation, hue, and sharpness control Complementary 5-line adaptive comb filters for both cross-luma and cross-chroma noise reduction Special architecture for locking to weak, noisy, or unstable signals Single 27.0 MHz or other common used crystal for all standards Internal phase-locked loop (PLL) for signal clock and sampling Subcarrier Genlock output for synchronizing color subcarrier of external encoder Standard programmable video output format: - CCIR 656 8-bit 4:2:2 with embedded syncs - 8-bit 4:2:2 with discrete syncs (CCIR 601) MacrovisionTM copy protection detection Power-on reset
1.2
Application
Following is a partial list of suggested application: Digital TV PDA Notebook PC Cellular phone Video recoder/player Internet/web appliances Handheld games Surveillance system Personal media player Video capture
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1.2
Analog Front-end Functional Block Diagram
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1.3
Chip Level Functional Block Diagram
Clamp I2C Control
Clamp
AGC Registers
ADC Scaler, timing and Clamp
PLL
YUV Separation and 5-line com filter Hue, Contrast, Brightness and Saturation Adjust YUV Gains constants
YUV to YCbCr Conversions
Scaler
Time Base Correction FIFO
I2C_DEV_ID decode
CCIR 656 Conversions, HSYNC, VSYNC, VBCLK and PCLK Bypass Logic
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1.4
Terminal Assignment
Pin #1: CVBSA/Y Pin #2: CVBSB/C Pin #3: AGND Pin #4: PLL_AVDD Pin #5: XTAL1 Pin #6: XTAL2 Pin #7: PLL_AGND Pin #8: RESETB Pin #9: PCLK/SCLK Pin #10: IO_DVDD Pin #11: YOUT(7)/I2CSEL Pin #12: YOUT(6) Pin #13: YOUT(5) Pin #14: YOUT(4) Pin #15: YOUT(3) Pin #16: YOUT(2)
Pin #17: YOUT(1) Pin #18: YOUT(0) Pin #19: DGND Pin #20: DVDD Pin #21: SCL Pin #22: SDA Pin #23: FID/GLCO Pin #24: VSYNC/PAL1 Pin #25: HSYNC Pin #26: AVID Pin #27: INTREQ/GPCL/ VBLK Pin #28: PDN Pin #29: REFP Pin #30: REFM Pin #31: CH_AGND Pin #32: CH_AVDD
1.5 Terminal Functions
TERMINAL NAME NUMBER
CVBSA/Y 1
TYPE
Analog Input
DESCRIPTION
Analog input. Connect to the video analog input via 0.1-F capacitor. The maximum input range is 0-1.2 VPP, and may require an attenuator to reduce the input amplitude to the desire level. If not used, connect to AGND via 0.1- F capacitor. Analog input. Connect to the video analog input via 0.1-F capacitor. The maximum input range is 0-1.2 VPP, and may require an attenuator to reduce the input amplitude to the desire level. If not used, connect to AGND via 0.1- F
CVBSB/C
2
Analog
Input
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AGND PLL_AVDD XTAL1 XTAL2 3 4 5 6
TYPE
DESCRIPTION
capacitor. Substrate. Connect to analog ground PLL power supply. Conncet to 1.8-V analog power supply External clock reference. XTAL1 can be connected to an oscillator or to one terminal of a crystal oscillator. XTAL2 may be connected to the other terminal of the crystal or not connected at all. One signal 27.0 MHz or other common used crystal is needed for CCIR 601 sampling, for all supported standards. PLL ground. Connect to analog ground Active-low reset. RESETB can be used only when PDN=1. When RESETB is pulled low, it resets all the registers. System Clock Digital power supply. Connect to 3.3 V I2CSEL: Determines the address for I2C (sampled during reset). 1 = Address is 0xBA 0 = Address is 0xB8 YOUT7: MSB of output decoded CCIR 656 output/YCbCr 4:2:2 output. Output decoded CCIR-656 output/YCbCr 4:2:2 output with discrete sync. Digital ground Digital power supply. Connect to 1.8-V digital power supply. I2C serial clock (open drain) I2C serial data (open drain) FID: Odd/even field indicator or vertical lock indicator. For the odd/even indicator, a 1 indicates the odd field. GLCO: This serial output carries color PLL information. A slave device can decode the information to allow chroma frequency control from the MIK2152 decoder. VSYNC: Vertical synchronization signal PALI: PAL line indicator or horizotal lock indicator For the PAL line indicator, a 1 indicates noninverted line, and a 0 indicates an inverted line. Horizotal synchronization signal Activate video indicator. The signal is high during the horizontal active time of the video output. INTREQ: Interrupt request output. GPCL: General-purpose control logic. This terminal has two functions: 1. General-purpose output. In this mode, the state of GPCL is dirrectly programmed vis I2C.
Analog Analog
Input Input Input Output
PLL_AGND RESETB PCLK/SCLK IO_DVDD YOUT(7)/I2CSEL
7 8 9 10 11
Analog Digital Digital Digital Digital
Input Input Output Input I/O
YOUT(6:0) DGND DVDD SCL SDA FID/GLCO
12-18 19 20 21 22 23
Digital Digital Digital Digital Digital Digital
I/O Input Input I/O I/O Output
VSYNC/PALI
24
Digital
Output
HSYNC AVID INTREQ/GPCL/ VBLK
25 26 27
Digial Digital Digital
Output Output I/O
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2.
DESCRIPTION
Vertical blank output. In this mode, the GPCL terminal is used to indicate the vertical blanking interval of the output video. The beginning and end times of this signal are programmed via I2C. Power-down signal (active low). Put the decoder in standby mode ADC reference power supply. Connect to analog ground through 1-F capacitor. ADC reference ground. Connect to analog ground through 1F capacitor. Analog ground Analog power supply. Connect to 1.8-V analog power supply
PDN REFP REFM CH_AGND CH_AVDD
28 29 30 31 32
Digital
Inputs Input Input
Analog Analog
Input Input
2. Internal Control Registers
ADDRESS 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h
DEFAULT 01h F8h A0h A2h 80h 00h 00h 00h B8h 0Ah 20h 00h 88h 00h 00h 00h 00h 03h ----00h
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W ----R/W
REGISTER FUNCTION Video input format control Brightness control Contrast control Saturation control Hue control Decoder operation I Decoder operation II AGC Adjustment and Clock Mode AGC control Color processing Clamp delay control Clamp position adjustment Reference settings U and V swap control Subcarrier phase adjustment System test mode Debug mode Digital clamp Reserved Reserved ADC gain and bias
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2.1 Register Definition 2.1.1 Reg_00 Video Input Format Control Register
Address Default 7 Bars[1:0] 00h 8'b00000001 6 5 PED 4 SVID[1:0] 3 2 MMode[1:0] 1 0 StdV
StdV=Reg_00[0] 1 : standard video input, (NTSC or PAL) 0 : for PAL(M) & PAL(Nc) MMode[1:0]=Reg_00[2:1]; MMode[1]=0 : auto-detected MMode[1]=1 : MMode[0]=0, PAL(Nc) or PAL, 625 lines depending on StdV MMode[0]=1, PAL(M) or NTSC, 525 lines depending on StdV Case of SVID[1:0]= 2'b11 : S-Video 2'b10 : Composite 2'b0x : Auto-detect PED=1 If PAL, black=64d If NTSC, black=72d PED=0 If PAL, black=64d If NTSC, black=61d Case of Bars[1:0]=Reg_00[7:6]; 2'b10 : display built-in 75% color bar 2'b11 : display built-in 100% color bar
2.1.2 Reg_01 Brightness Control Register
Address Default 01h 8'b11111000
Brit = Reg_01[7:0]; signed; default = F8h
2.1.3 Reg_02 Contrast Control Register
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Address Default 02h 8'b10100000
Cont = Reg_02[7:0]; unsigned; default = A0h
2.1.4 Reg_03 Saturation Control Register
Address Default
03h 8'hA2
Satur = Reg_03[7:0]; unsigned; default = A2h
2.1.5 Reg_04 Hue Control Register
Address Default 04h 8'h80
Hue = Reg_04[7:0]; unsigned; default = 80h
2.1.6 Reg_05 Decoder Operation Control Register I
Address Default 7 05h 8'd0 6 5 4 3 VFM[5:0] manual fader control for upper line/lower line fader 2 1 DMode[1:0] 0
Case DMode[1:0]= 0x : 5 line; 10 : 3 line; 11 : 1 line (bandpass) Case VFM[5]= 0 : Fade Value is automatic; 1 : Fade Value = VFM[4:0]
2.1.7 Reg_06 Decoder Operation Control Register II
Address Default 7 06h 8'd0 6 5 4 3 SLM[5:0] manual fader control for single line/comb fader 2 1 FM[1:0] 0
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Case of FM[1:0]= 2'b0x : auto-detect 2'b10 : wide 2'b11 : narrow Case SLM[5]= 0 : Fade Value is automatic; 1 : Fade Value = SLM[4:0]
2.1.8 Reg_07 AGC Adjustment and Clock Mode Register
Address Default 7 CMode 07h 8'd0 6 5 InvClamp 4 soft_rst 3 NoBlue 2 XCAGC 1 XSAGC 0 XAGC
XAGC=Reg_07[0]: set to disable automatic gain adjustment (AGC); XSAGC=Reg_07[1]: set to disable automatic adjustment of Sync Error (SAGC); XCAGC=Reg_07[2]: set to disable automatic adjustment of Chroma (CAGC); NoBlue=Reg_07[3]: set to disable insertion of blue screen; soft_rst=Reg_07[4]: Software reset, active high; after program to 1, then must program to 0 InvClamp=Reg_07[5]: Invert Clamp signal; CMode[1:0]=Reg_07[7:6] Clock mode Case of 00 : 54 MHz clock and data 01 : 54 MHz clock and 27 MHz data 1x : 27 MHz clock and data
2.1.9 Reg_08 AGC Control Register
Address Default 7 08h 8'hB8 6 5 4 AGC0[7:0] AGC0 = Reg_08[7:0]; default AGC gain; 3 2 1 0
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2.1.10 Reg_09 Color Processing Register
Address Default 7 CCor[1:0] CDly[3:0] = Reg_09[3:0] 09h 8'h0A 6 5 SbcAdj0[1:0] adjust chroma to luma delay; default = 10d 4 3 2 CDly[3:0] 1 0
SbcAdj0[1:0] = Reg_09[5:4] adjust phase of subcarrier for NTSC; default = 0 CCor[1:0] = Reg_09[7:6] control color correction 00: PAL 01: always 1x: never
2.1.11 Reg_0A Clamp delay Control Register
Address Default 0Ah 8'h20
CDelay = Reg_0A[7:0]; adjust delay of falling edge of Clamp; default =32d
2.1.12 Reg_0B Clamp Position Adjustment Register
Address Default 0Bh 8'd0
CDstart = Reg_0B[7:0]; value to adjust clamp position
2.1.13 Reg_0C Reference Settings Register
Address Default 7 0Ch 8'h88 6 BLimit[3:0] 5 4 3 2 SSlice[3:0] 1 0
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SSlice[3:0] = Reg_0C[3:0] slicing level of sync for FPGA control; default = 8
BLimit[3:0] = Reg_0C[7:4] used in identifying unstable burst for FPGA control; default = 8
2.1.14 Reg_0D U and V Swap Control Register
Address Default 7 --0Dh 8'd0 6 --5 --4 --3 --2 1 SwpUV[2:0] 0
Case of SwpUV[2:0]= 3'b000 : No swap 3'b001 : swap UV when composite and PAL; 3'b010 : swap UV when composite and NTSC; 3'b011 : swap UV when composite; 3'b100 : swap UV; 3'b101 : swap UV when S-Video and PAL; 3'b110 : swap UV when S-Video and NTSC; 3'b111 : swap UV when S-Video;
2.1.15 Reg_0E Subcarrier Phase Adjustment Register
Address Default 0Eh 8'd0
when Composite and NTSC SbcAdj taken from reg_OE[1:0] when Composite and PAL SbcAdj taken from reg_OE[3:2] when S-Video and NTSC SbcAdj taken from reg_OE[5:4] when S-Video and PAL SbcAdj taken from reg_OE[7:6]
2.1.16 Reg_0F System Test Mode Register
Address Default 7 0Fh 8'h0 6 5 4 3 2 1 0
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TSel[3:0] TSel[3:0] = Reg_0F[7:4] Used to select test TOSel[3:0]
TOSel[3:0] = Reg_0F[3:0] Used to select outputs in Test Mode
2.1.17 Reg_10 Debug Mode Control Register
Address Default 7 10h 8'h00 6 5 Channel_B 4 adc_sv_B 3 digital_debug 2 pd_pll 1 pd_xtal 0 adc_debug
adc_debug = Reg_10 [0]; adc debug mode pd_xtal = Reg_10 [1]; set to power-down the crystal oscillator for IDDQ test pd_pll = Reg_10 [2]; set to power-down and bypasses the PLL. In this mode the crystal input goes directly to the ADC clock, so an external 54 MHz clock can be used to drive the ADC and bypass the PLL. This is also for IDDQ test digital_debug = Reg_10 [3]; by-pass adc; input to digital section directly adc_sv_B = Reg_10 [4]; set to output S-video portB(C) signal ChannelB = Reg_10 [5]; set to select port B
2.1.18 Reg_11 Digital Clamp Control Register
Address Default 7 11h 8'h03 6 5 4 3 2 1 DClamp [2:0] 0
DClamp [0]: set, disable analog clamp; DClamp [1]: set, enable digital clamp on composite or Y of S-video DClamp [2]: set, enable digital clamp on chroma, C of S-video
2.1.20 Reg_14 ADC Gain and Bias Control Register
Address Default 7 14h 8'h00 6 5 ADC_GAIN[3:0] 4 3 2 1 ADC_BIAS[3:0] 0
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ADC_GAIN[3:0] = Reg_14[7:4] ADC_BIAS[3:0] = Reg_14[3:0]
ADC_GAIN for ADC ADC_BIAS for ADC
3. Electrical Specifications
3.1 Absolute Maximum Ratings Over Operating Free-Air Temperature Range
IOVDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 4.5 V DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 2.3 V PLL_AVDD to PLL_AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 2.3 V CH1_AVDD to CH1_AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 2.3 V Digital input voltage range, Vl to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 4.5 V Input voltage range, XTAL1 to PLL_GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 2.3 V Analog input voltage range Al to CH1_AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 2.0 V Digital Output voltage range, VO to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 4.5 V Operating free-air temperature, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 70oC Supply voltage range:
3.2
Recommended Operating Conditions
IODVDD DVDD PLL_AVDD CH1_AVDD VI(P-P) VIH VIL VIH_XTAL VIL_XTAL IOH IOL IOH_SCLK IOL_SCLK TA
Digital I/O supply voltage Digital supply voltage Analog PLL supply voltage Analog core supply voltage Analog input voltage (ac-coupling necessary) Digital input voltage high Digital input voltage low XTAL input voltage high XTAL input voltage low High-level output current Low-level output current SCLK high-level output current SCLK low-level output current Operating free-air temperature
MIN 3.0 1.65 1.65 1.65 0 0.7 IOVDD 0.7 PLL_AVDD
TYP 3.3 1.8 1.8 1.8
MAX 3.6 2.0 2.0 2.0 1.0 0.3 IOVDD 0.3 PLL_AVDD 2 -2 4 -4 70
0
UNIT V V V V V V V V V mA mA mA mA o C
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4. Packaging
32-pin TQFP
Unit: All linear dimensions are in millimeters.
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